Technical Field
The present disclosure relates to dual gate transistors built on substrates having a buried oxide layer and, in particular, to the use of such dual gate transistors in integrated circuits to improve circuit performance.
Description of the Related Art
Integrated circuits typically incorporate N-doped and P-doped metal oxide semiconductor field effect transistor (MOSFET) devices in which current flows through a semiconducting channel between a source and a drain, in response to a bias voltage applied to a gate. When the applied voltage exceeds a characteristic threshold voltage Vt, the device switches on. Ideally, such a switch: a) passes zero current when it is off; b) supplies large current flow when it is on; and c) switches instantly between the on and off states. Unfortunately, a transistor is not ideal as constructed in an integrated circuit and tends to leak current even when it is off. Current that leaks through, or out of, the device tends to drain the battery that supplies power to the device.
For many years, integrated circuit transistor performance was improved by shrinking critical dimensions to increase switching speed. However, as dimensions of silicon-based transistors continue to shrink, maintaining control of various electrical characteristics, including off-state leakage, becomes increasingly more challenging, while performance benefits derived from shrinking the device dimensions have become less significant. It is therefore advantageous, in general, to increase switching speed and to reduce leakage current in the transistor by alternative means, including changes in materials and device geometry.
One technology that has been developed to control current leakage is the silicon-on-insulator (SOI) transistor. Examples of conventional planar (2-D) SOI transistor structures built on substrates having a buried oxide (BOX) layer are shown in FIGS. 1A and 1B and described below in greater detail. To provide better control of the current flow in the channel, dual gate SOI transistors have been developed, such as the exemplary dual gate SOI transistor shown in FIG. 2, described in U.S. Patent Publication No. 2010/0264492. A dual gate transistor is an electronic switching device in which current flow within the semiconducting channel of a traditional FET is controlled by two gates instead of one, so as to influence the current flow from two opposing surfaces instead of one.
Extending this idea further, 3-D tri-gate transistors have been developed in which the planar semiconducting channel of a traditional FET is replaced by a 3-D semiconducting fin that extends outward, normal to the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence the current flow from three surfaces instead of one or two. The improved control achieved with such dual gate and tri-gate designs results in lower threshold voltages, faster switching performance, and reduced current leakage.